| Start Date: | 2025-01-13 | Course Code: | CS-205 | L-T-P-C: | 3-1-0-0 |
|---|---|---|---|---|---|
| Course Name: | Computer Architecture And Organization | Semester: | 4 | Course Faculty: | Debbrota Paul Chowdhury |
Course Plan
|
Session No |
Topics to be covered |
Time in min |
Ref. Book |
Teaching Method |
|
1,2 |
Define Basic architecture of Computer, Von Neumann architecture |
100 |
T1 |
L/T |
|
3,4 |
Computer organization ,Computer Register architecture |
100 |
T1 |
L/T |
|
5 |
Computer Bus Architecture, Address bus, Data bus, Control bus |
100 |
T1 |
L/T |
|
6 |
Memory Hierarchical Structure |
50 |
T1 |
L/T |
|
7 |
Introduction,Stack organization,Memory Stack |
100 |
T1 |
L/T |
|
8,9 |
Instruction Format, Three Address instruction ,Two address instruction, one address instruction, Zero address instruction (numeric example) |
100 |
T1 |
L/T |
|
10,11 |
Addressing Modes with numerical Example |
100 |
T1 |
L/T |
|
12 |
Instruction Cycle (Fetch operation,decode,execute operation) |
50 |
T1 |
L/T |
|
13,14 |
Instruction Types, Memory reference instruction, Input-output instruction, processor instruction and register reference instruction |
100 |
T1 |
L/T |
|
15,16 |
Fixed point and floating point arithmetic, flow chart of ADD,SUB,MUL,DIV arithmetic operation, |
100 |
T1 |
L/T |
|
17 |
Booth Multiplication Algorithm with numeric Example. |
50 |
T1 |
L/T |
|
18 |
Class Test-I |
|||
|
19 |
Introduction of Controller, Basic Controller design ,Control Memory |
50 |
T1 |
L/T |
|
20,21 |
Hardwired Control organization , and different Design and operations on Hardwired Control unit |
100 |
T1 |
L/T |
|
22 |
Micro program and micro instruction |
50 |
T1 |
L/T |
|
23 |
Microprgramed control unit, micro program sequencer |
50 |
T1 |
L/T |
|
24 |
Basic introduction of all memory like-primary memory(RAM,ROM) Secondary memory, Cache Memory, associative memory ,virtual memory |
50 |
T1 |
L/T |
|
25,26 |
Main memory ,RAM Chip diagram ,ROM Chip Diagram, Memory Connection with processor, Types of RAM and ROM |
100 |
T1 |
L/T |
|
27,28 |
Cache Memory ,Cache operation, Hit Ratio, Average Cache access time (numeric Example) |
100 |
T1 |
L/T |
|
29,30 |
Cache Mapping, Associative mapping, Direct mapping, Set associative mapping with numeric example |
100 |
T1 |
L/T |
|
31 |
Auxiliary Memory (magnetic Disk and Magnetic Tape) |
50 |
T1 |
L/T |
|
32,33 |
Virtual memory concept, Paging ,Segmentation, Page Replacement Technique |
100 |
T1 |
L/T |
|
34 |
Class Test-II |
|||
|
35 |
Define Basic Peripheral Devices, input peripheral, output peripherals |
50 |
T1 |
L/T |
|
36,37 |
Input-Output Transfer, Input-Output Interface, Various I/O Command |
100 |
T1 |
L/T |
|
38 |
Asynchronous Data Transfer, Strobe Control and Hand shaking mechanism, Serial Asynchronous Transfer |
50 |
T1 |
L/T |
|
39,40 |
Modes of Transfer (Programmed I/O ,Interrupt Initiated I/O,DMA ) ,Priority Intrrupt,Daisy Chain Priority Interrupt |
100 |
T1 |
L/T |
|
41 |
DMA Transfer and DMA Controller |
50 |
T1 |
L/T |
|
42 |
Class Test-III |
|
TEXT BOOKS
1. “Computer system Architecture”, M.Morris Mano, Pearson Education.
2. “Computer Organization and Design”, David A.Patterson, John L. Hennessy ARM Edition.
3. “Computer System Organization & Architecture”, John D.Carpinelli.
4. “Computer Architecture and organization”, Hayes (TMH)
Class Notes & PPTs
- - PPT
